Based on idealized interconnect scaling rules, we derive the optimal distribution of linewidths as a function of length for wire-limited layouts utilizing RC-limited interconnections. We show that the width of the wires should be chosen proportional to the cube root of their length for two-dimensional layouts and proportional to the fourth root of their length for full three-dimensional layouts so as to minimize average signal delay. © 1993 Taylor & Francis Ltd
Conditions are outlined under which propagation delays in VLSI circuits can be achieved that are log...
The lithography used for 32 nanometers and smaller VLSI process technologies restricts the admissibl...
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI...
The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown t...
Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and th...
Abstrnct-The propagation delay of interconnection lines is a major factor in determining the perform...
In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be th...
With feature sizes decreasing and chip area increasing it becomes more and more time consuming to tr...
Abstract—This paper addresses the critical problem of global wire optimization for nanometer scale v...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
In a parallel multiwire structure, the exact spacing and size of the wires determine both the resist...
In deep sub-micron (DSM) circuits proper analysis of interconnect delay is very important. When rela...
Due to the continue trend of technology for circuit scaling; optimal sizes for transistors and cable...
The problem of optimal space allocation among interconnecting wires of VLSI chips, in order to minim...
An e#cient solution to the wire sizing problem #WSP# using the Elmore delay model is proposed. Two f...
Conditions are outlined under which propagation delays in VLSI circuits can be achieved that are log...
The lithography used for 32 nanometers and smaller VLSI process technologies restricts the admissibl...
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI...
The optimum wire shape to produce the minimum signal propagation delay across an RLC line is shown t...
Conventional methods for optimal sizing of wires and transistors use linear RC circuit models and th...
Abstrnct-The propagation delay of interconnection lines is a major factor in determining the perform...
In this paper, we consider non-uniform wire-sizing. Given a wire segment of length L, let f(x) be th...
With feature sizes decreasing and chip area increasing it becomes more and more time consuming to tr...
Abstract—This paper addresses the critical problem of global wire optimization for nanometer scale v...
In this paper, we study the optimal wiresizing problem under the distributed Elmore delay model. We ...
In a parallel multiwire structure, the exact spacing and size of the wires determine both the resist...
In deep sub-micron (DSM) circuits proper analysis of interconnect delay is very important. When rela...
Due to the continue trend of technology for circuit scaling; optimal sizes for transistors and cable...
The problem of optimal space allocation among interconnecting wires of VLSI chips, in order to minim...
An e#cient solution to the wire sizing problem #WSP# using the Elmore delay model is proposed. Two f...
Conditions are outlined under which propagation delays in VLSI circuits can be achieved that are log...
The lithography used for 32 nanometers and smaller VLSI process technologies restricts the admissibl...
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI...