Efficiency Enhancement of GaN Power Amplifiers over Wide Bandwidth by an Active Control of Gate Source Waveforms

This paper presents a technique to improve the power added efficiency (PAE) of GaN power amplifiers by an appropriate shaping of the gate source voltage waveform. High efficiency performances of microwave power amplifiers are reached by implementing proper matching conditions at harmonic components. For microwave applications, harmonic tuned amplifiers offer for the moment the best energy conversion efficiency between DC supply and RF power at fundamental frequency available in a 50 load.[1] In addition to proper harmonic terminations, the minimization of power losses at fundamental frequency in the output RF matching and power combining circuit is of prime importance. This has been widely reported over the past few years. Considering this main aspect GaN technology offers an evident advantage due to its high drain voltage operation capability that is beneficial for designing low loss and wideband output matching circuits. Several works have been reported during the past few years.[2],[3],[4],[5],[6] A problem encountered when designing high efficiency power amplifiers is to avoid getting high efficiency performances restricted to only a narrow frequency bandwidth around center frequency. It can be often observed that the higher the PAE is at center frequency, the quicker the PAE decreases at offset frequencies each side away from the center frequency. This can be attributed to high Q resonant tuning conditions. We point out and examine in this paper a major role played by the gate source voltage waveform in PAE performances over a frequency bandwidth of interest. For power amplifiers operating at saturated power, a significant second harmonic current component exists at the gate port and is terminated into a passive resonant circuit like for example a quarter wave length line used in the gate bias circuit. For offset frequencies, phase conditions of the passive source impedance at second harmonic vary and lead to non appropriate enlarged gate source voltage waveform upper the pinch off value.That leads to larger turn on time of the drain current resulting in a larger overlapping between drain current and drain voltage prejudicial for dissipated power and power added efficiency. In this paper we present a solution to maintain an appropriate gate source voltage shape. It consists in driving the gate of a power stage with an appropriate half sine voltage shape supplied by a driver stage operating at low drain bias voltage