Scaling of analog LDPC decoders in sub-100nm CMOS processes

International audienceAnalog implementations of digital error control decoders, generally referred to as analog decoding, have recently been proposed asan energy and area competitive methodology. Despite several successful implementations of small analog error control decoders, little is currently known about how this methodology scales to smaller process technologies and copes with the non-idealities of nano-scale transistor sizing. A comprehensive analysis of the potential of sub-threshold analog decoding is examined in this paper. It is shown that mismatch effects dominated by threshold mismatch impose firm lower limits on the sizes of transistors. The effect of various forms of leakage currents is also investigated and minimal leakage current to normalizing currents are found using density evolution and control simulations. Finally, the convergence speed of analog decoders is examined via a density evolution approach. The results are compiled and predictions are given which show that process scaling below 90nm processes brings no advantages, and, in some cases, may even degrade performance or increase required resources