High-Level Synthesis: On the Path to ESL Design

International audienceIn the SoCs context, the traditional IC design methodology relying on EDA tools used in a two stages design flow -a VHDL/Verilog RTL specification, followed by logical and physical synthesis- is no more suitable. Designing MPSoC requires new design approaches raising the specification abstraction up to Electronic System Level (ESL). Hence, virtual prototyping, design space exploration and high-level/system synthesis with the goal of optimised and functionally correct product implementation are needed. In this paper, we present the High-Level Synthesis (HLS) tool named GAUT. From a bit-accurate C/C++ specification and a set of design constraints, GAUT automatically generates a potentially pipelined RTL architecture described in both VHDL and a SystemC respectively used for synthesis and virtual prototyping. Results demonstrate the interest of our approach on a MJPEG application and its capability in exploring various SoC design tradeoffs