Compaction of decision diagrams for describing multi-process VHDL descriptions

ISBN: 9985590813A method is presented for compressing decision diagrams (DD) created for multi-process VHDL descriptions with the goal of functional test generation. Each process is represented either by one DD or a set of DDs. The fine-grained timing model is replaced by a coarse timing model which helps to reduce the complexity of test generation. A set of rules for compressing the DD model is given. The method is illustrated by example. Experimental data to prove the efficiency of test generation based on compressed DDs is presented