Optimized synthesis of dedicated controllers with concurrent checking capabilities

The authors present a novel synthesis method of dedicated controllers which aims at the detection of faults which cause errors in the state sequences. The state code flow is compacted through polynomial division. An implicit `justifying signature' method is applied at the state code level and ensures identical signatures before each join node of the control flow graph. The signatures are then independent of the path followed previously in the graph, and the comparison with reference data is greatly facilitated. This property is obtained by a clever state assignment, nearly without area overhead. The controllers can therefore be checked by signature analysis, either by a built-in monitor or by an external checker. The software implementation of the synthesis tool is presented, and the hardware implementation of the concurrent checking is described