Built-in concurrent checking of ASICs

This paper focuses on the implementation on silicon of concurrent test facilities in ASICs. The concurrent checking method employed here is based on signature analysis because of its global low cost (hardware, area, complexity, . . .) and its high detection capability. Details on signature analysis and instruction flow compaction are recalled and two applications are given. The former is the actual implementation of this principle in an application specific microprocessor and the later extends it to dedicated controllers. For dedicated controllers, two approaches are presented. The first one applies the machine level approach to a lower level. The second one is very original as it takes profit of the synthesis of the controller to introduce checking capabilities nearly without overhead