International audienceThe high cost for testing the analog blocks of a modern chip has sparked research efforts to replace the standard tests with less costly alternative tests. However, test engineers are rather reluctant to adopt alternative tests unless they are evaluated thoroughly before moving to production and they are proven to maintain test quality. This paper gives a comprehensive overview of statistical techniques based on density estimation for evaluating analog parametric test metrics during the test development phase. A large-scale simulation study is carried out for the first time with the aim to demonstrate these techniques in action
International audienceThe estimation of test metrics such as defect level, test yield or yield loss ...
ISBN: 0-7803-9726-6The estimation of test metrics such as defect level, test yield or yield loss is ...
International audienceThe estimation of test metrics such as defect level, test yield or yield loss ...
International audienceThe high cost for testing the analog blocks of a modern chip has sparked resea...
International audienceThe high cost for testing the analog blocks of a modern chip has sparked resea...
ISBN 978-1-4673-6038-8International audienceThe high cost for testing the analog blocks of a modern ...
ISBN 978-1-4673-6038-8International audienceThe high cost for testing the analog blocks of a modern ...
ISBN 978-1-4673-6038-8International audienceThe high cost for testing the analog blocks of a modern ...
ISBN 978-1-4673-6038-8International audienceThe high cost for testing the analog blocks of a modern ...
International audienceThe high cost for testing the analog blocks of a modern chip has sparked resea...
© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
International audienceThe high cost of testing certain analog, mixed-signal, and RF circuits has dri...
International audienceThe high cost of testing certain analog, mixed-signal, and RF circuits has dri...
International audienceThe estimation of test metrics such as defect level, test yield or yield loss ...
ISBN: 0-7803-9726-6The estimation of test metrics such as defect level, test yield or yield loss is ...
International audienceThe estimation of test metrics such as defect level, test yield or yield loss ...
International audienceThe high cost for testing the analog blocks of a modern chip has sparked resea...
International audienceThe high cost for testing the analog blocks of a modern chip has sparked resea...
ISBN 978-1-4673-6038-8International audienceThe high cost for testing the analog blocks of a modern ...
ISBN 978-1-4673-6038-8International audienceThe high cost for testing the analog blocks of a modern ...
ISBN 978-1-4673-6038-8International audienceThe high cost for testing the analog blocks of a modern ...
ISBN 978-1-4673-6038-8International audienceThe high cost for testing the analog blocks of a modern ...
International audienceThe high cost for testing the analog blocks of a modern chip has sparked resea...
© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
© 2011 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for a...
International audienceThe high cost of testing certain analog, mixed-signal, and RF circuits has dri...
International audienceThe high cost of testing certain analog, mixed-signal, and RF circuits has dri...
International audienceThe estimation of test metrics such as defect level, test yield or yield loss ...
ISBN: 0-7803-9726-6The estimation of test metrics such as defect level, test yield or yield loss is ...
International audienceThe estimation of test metrics such as defect level, test yield or yield loss ...