During neutron irradiation of 4-Mb SRAMs, large-scale multiple cell upsets (MCUs) were observed. These were observed in 90-nm devices at accelerated test facilities providing fission, fusion, and spallation neutron environments. The MCUs are shown to manifest themselves in 2-D patterns encompassing scores of cells, which, even with bit interleaving, lead to uncorrectable multiple bit upsets (MBU) in the same word. The mechanism behind the MCU appears to be micro-latching within blocks of the memory array that are powered up sequentially during the read cycle of the device. © 1963-2012 IEEE
IEEE Catalog Number: CFP15449-ART (XPLORE) ISBN: 978-1-5090-0232-0 (XPLORE) IEEE Catalog Number: CFP...
Recently, the occurrence of multiple events in static tests has been investigated by checking the st...
Single event upset (SEU) is mainly caused by neutrons in the terrestrial environment. In addition, S...
International audienceDownscaling of devices increases the Multiple-Cell-Upset (MCU) cross section o...
International audienceWhile single bit upsets on memories and storage elements are mitigated with ei...
This paper presents an analysis of the multiple events (and more specifically, Multiple Cell Upsets ...
Various SRAM and MOSFET devices were exposed to 3 MeV and 14 MeV neutrons at a fusion facility and t...
International audienceThis paper presents a new 3D methodology to simulate Multiple Bit Upsets in co...
This paper presents an approach to discern MCUs from SEUs in SRAM memories. Experiments involving ra...
This study analyses the response of synchronous dynamic random access memories to neutron irradiatio...
Reliability is a critical issue for memories. Radiation particles that hit the device can cause erro...
We analyzed floating-gate upsets in 25-nm multilevel cell NAND Flash memories irradiated with heavy ...
As an important spaceborne electronic device, the static random access memory (SRAM) device is inevi...
International audienceA sensitivity characterization of a Xilinx Artix-7 field programmable gate arr...
Abstract—This paper proposes a technique that mitigates multi-bit-upset (MBU) in multi-bit-latch (MB...
IEEE Catalog Number: CFP15449-ART (XPLORE) ISBN: 978-1-5090-0232-0 (XPLORE) IEEE Catalog Number: CFP...
Recently, the occurrence of multiple events in static tests has been investigated by checking the st...
Single event upset (SEU) is mainly caused by neutrons in the terrestrial environment. In addition, S...
International audienceDownscaling of devices increases the Multiple-Cell-Upset (MCU) cross section o...
International audienceWhile single bit upsets on memories and storage elements are mitigated with ei...
This paper presents an analysis of the multiple events (and more specifically, Multiple Cell Upsets ...
Various SRAM and MOSFET devices were exposed to 3 MeV and 14 MeV neutrons at a fusion facility and t...
International audienceThis paper presents a new 3D methodology to simulate Multiple Bit Upsets in co...
This paper presents an approach to discern MCUs from SEUs in SRAM memories. Experiments involving ra...
This study analyses the response of synchronous dynamic random access memories to neutron irradiatio...
Reliability is a critical issue for memories. Radiation particles that hit the device can cause erro...
We analyzed floating-gate upsets in 25-nm multilevel cell NAND Flash memories irradiated with heavy ...
As an important spaceborne electronic device, the static random access memory (SRAM) device is inevi...
International audienceA sensitivity characterization of a Xilinx Artix-7 field programmable gate arr...
Abstract—This paper proposes a technique that mitigates multi-bit-upset (MBU) in multi-bit-latch (MB...
IEEE Catalog Number: CFP15449-ART (XPLORE) ISBN: 978-1-5090-0232-0 (XPLORE) IEEE Catalog Number: CFP...
Recently, the occurrence of multiple events in static tests has been investigated by checking the st...
Single event upset (SEU) is mainly caused by neutrons in the terrestrial environment. In addition, S...