An Efficient Hardware Architecture for Multilayer Spiking Neural Networks

Spiking Neural Network (SNN) is the most recent computa tional model that can emulate the behaviors of biological neuron system. This paper highlights and discusses an efficient hardware architecture for the hardware SNNs, which includes a layer-level tile architecture (LTA) for the neurons and synapses, and a novel routing architecture (NRA) for the interconnections between the neuron nodes. In addition, a visu alization performance monitoring platform is designed, which is used as functional verification and performance monitoring for the SNN hard ware system. Experimental results demonstrate that the proposed archi tecture is feasible and capable of scaling to large hardware multilayer SNNs