Charged particle induced soft errors in 1 Mbit and 4 Mbit drams as the basis for a portable radiation detector system.

A portable high speed digital electronic DRAM radiation detection system was designed and constructed at the University of Surrey. The electronics system was designed around a Fully Programmable Gate Array (FPGA) acting as the DRAM controller. The system was controlled by a Personal Computer (PC) which also acquired and stored the data. The system control software was developed using the C language and written at the University of Surrey, the system was designed for use with 4 different types of Dynamic Random Access Memory (DRAM) chips acting as detectors mounted on separate boards from the controller. This was so that the main electronics could be placed in a shielded area whilst the detector is exposed to a radiation field. This is especially important in neutron fields where activation of components can be a significant problem. The radiation response of decapsulated 1 Mbit and 4 Mbit DRAMs to alpha particles was examined. There were six different devices in all, three 1 Mbit standard power devices, two 4 Mbit standard power devices and one 4 Mbit low power DRAM. These DRAMs were tested under different operating conditions of operating voltage, memory data pattern, cycle time and incident a-particle energy. Each DRAM was examined and their peak responses in terms of these factors was determined and compared to previous experiments with earlier DRAMs, all six devices were found to show an increase in soft error rate (SER) when the operating voltage of the DRAM was decreased. This was in agreement with previous experiments. This continued until an optimum was reached, if the operating was decreased below the optimum then the SER of the devices would quickly fall to zero, which was an unexpected effect. Two devices, the Hyundai 1 Mbit device and the Hitachi 4 Mbit ZIG-ZAG device exhibited a strong dependence on memory pattern with the Hyundai having no response with a 0000 pattern and a peak SER with a 1111 pattern. The Hitachi device had it's highest SER at 0000 and it's lowest at 1111. The other devices all exhibited some pattern dependence but it was not as marked as in these two devices. The devices all showed a lower SER for higher energy alpha particles (~5 MeV) with the SER increasing as the incident alpha particle energy decreased until a maximum SER was reached. As the incident energy was decreased further the SER would begin to fall again. This was also in agreement with previous DRAM experiments. The highest SER of the DRAMs tested was that of the 4 Mbit low power DRAM (manufactured by Toshiba), which had an SER of 224.25 s-1, more than 25 times that of the next most sensitive device, the 1 Mbit Hyundai standard power DRAM with a peak SER of 8.27 s-1. Unfortunately, due to an undetected fault in the low power header board the Toshiba device was not available to be used in the positron and neutron experiments. The 1 Mbit standard power devices (as they were more sensitive than the 4 Mbit standard power devices) were taken to the MRC Cyclotron Unit in London to try and detect a variety of positron emitters (11C, 15O, 18F 68Ge). Unfortunately, these experiments were not successful and the 1 Mbit devices did not appear to have enough sensitivity to be able to detect any of these particles. The 1 Mbit devices were also taken and irradiated in a neutron beam from the CONSORT-II research reactor at Imperial College, the devices were irradiated both bare and coated with a thermal neutron to charged particle converter material, the converter used was 6LiF and was deposited directly onto the bare silicon die of the DRAM, in both cases thermal neutrons were detected by the DRAMs. Further possible experiments with a larger range of low power DRAMs to investigate their apparently high SER rates are discussed, including further experiments with positrons and neutrons. The implications of further miniaturisation of the controller and header boards for remote inspection purposes are also discussed