Add to ORKGSilicon on insulator (SOI - Smartcut(R)) wafers were implanted with 1MeV and 300keV silicon ions to doses of 3.8x10(15) cm(-2) and 3x10(14) cm(-2), respectively, in order to modify the vacancy concentration in a controlled way. Boron was then implanted at 2keV to a dose of 1x10(15) cm(-2) into the near-surface part of the vacancy-engineered region. Atomic profiles were determined using SIMS and electrical profiles were measured using a novel Differential Hall Effect (DHE) technique, which enables profiling of electrically active dopants with a nanometer depth resolution. The electrical profiles provide pairs of carrier concentration and mobility values as a function of depth. The buried oxide (BOX) is proven to restrict the back diffusing i...
A differential Hall effect technique has been developed to obtain doping profiles at a depth resolut...
The redistribution during annealing of low-energy B implants in SOI structures and in bulk Si have b...
To continue the scaling down of CMOS devices, high doped ultra-shallow source/drain junctions must b...
Formation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next g...
P -type ultrashallow junctions are widely fabricated using Ge preamorphization prior to ultralow-ene...
For the next generation of electronic products, transistors need to be reduced in size and are requi...
For CMOS technology, generations beyond the 65 nm node a major goal is achieving highly activated, u...
P-type ultrashallow junctions are widely fabricated using Ge preamorphization prior to ultralow-ener...
The fabrication of preamorphized p-type ultrashallow junctions in silicon-on-insulator (SOI) has bee...
The fabrication of preamorphized p-type ultrashallow junctions in silicon-on-insulator (SOI) has bee...
For the last 40 years a natural demand for faster, more complex, and therefore, more functional elec...
International audienceLow-energy implantation is one of the most promising options for ultrashallow ...
The formation of boron interstitial clusters is a key limiting factor for the fabrication of highly-...
As the CMOS transistor scaling is approaching its physical limits, the semiconductor industry is for...
Forming highly conducting, ultra-shallow boron doped layers, is well known to be a challenge for fut...
A differential Hall effect technique has been developed to obtain doping profiles at a depth resolut...
The redistribution during annealing of low-energy B implants in SOI structures and in bulk Si have b...
To continue the scaling down of CMOS devices, high doped ultra-shallow source/drain junctions must b...
Formation of highly activated, ultra-shallow and abrupt profiles is a key requirement for the next g...
P -type ultrashallow junctions are widely fabricated using Ge preamorphization prior to ultralow-ene...
For the next generation of electronic products, transistors need to be reduced in size and are requi...
For CMOS technology, generations beyond the 65 nm node a major goal is achieving highly activated, u...
P-type ultrashallow junctions are widely fabricated using Ge preamorphization prior to ultralow-ener...
The fabrication of preamorphized p-type ultrashallow junctions in silicon-on-insulator (SOI) has bee...
The fabrication of preamorphized p-type ultrashallow junctions in silicon-on-insulator (SOI) has bee...
For the last 40 years a natural demand for faster, more complex, and therefore, more functional elec...
International audienceLow-energy implantation is one of the most promising options for ultrashallow ...
The formation of boron interstitial clusters is a key limiting factor for the fabrication of highly-...
As the CMOS transistor scaling is approaching its physical limits, the semiconductor industry is for...
Forming highly conducting, ultra-shallow boron doped layers, is well known to be a challenge for fut...
A differential Hall effect technique has been developed to obtain doping profiles at a depth resolut...
The redistribution during annealing of low-energy B implants in SOI structures and in bulk Si have b...
To continue the scaling down of CMOS devices, high doped ultra-shallow source/drain junctions must b...