Source-Gated Transistors Based on Solution Processed Silicon Nanowires for Low Power Applications

The solution-based assembly of field-effect transistors using nanowire inks, processed at low temperatures, offers an enormous potential for low power applications envisioned for the “Internet of Things,” including power management sensor circuits and electronics for in vivo bioimplants. Such low-temperature assembly, however, yields substantial contact potential barriers, with limited capacity for high current applications. In this study, the Schottky effect in a specific transistor configuration is utilized to achieve much reduced power consumption, with low saturation voltages (≈1 V), with relatively thick 230-nm SiO2 dielectrics. These source-gated transistors (SGTs) employ solution-deposited silicon nanowire arrays. A range of metal electrode work functions are investigated as device contacts and SGT operation is realized only in the structures with high source contact barriers. Such devices show very early drain current pinch-off, abruptly saturating at low drain voltages. The authors show that drain-current modulation is achieved via the gate field acting on the source barrier and lowering it through image force effects. Activation energy measurements reveal gate-induced source barrier lowering of ≈3 meV V−1. Numerical simulations show excellent correlation with the experimental data. These features, coupled with flat current saturation characteristics, are ideal for a range of low power applications, including wearable electronics and autonomous systems