Low-Power Wireless Body Area Sensor Network Communication Sub-Systems.

As we move towards the nanotechnology era, technological advancements in the fine line-width submicron CMOS process has allowed vast improvements in the area of digital VLSI. The continually increasing level of integration with steadily rising clock rates is paving a path in the direction of more sophisticated and powerful digital systems. The primary technology that has been benefited from these advances is the wireless body area sensor networks technology (WBASN). The concept of WBASN has been introduced recently in biomedical application where miniaturized wearable or implantable wireless sensors are used for continuous monitoring of patients. These sensor nodes are typically capable of wireless communication and are significantly constrained in the amount of available resources such as power consumption, storage and computation. In order to make wireless body area sensor networks cost-effective and practical, the electronic components of a wireless sensor node need to run for months to years on the same battery. In this work there were two general thrusts of this research: The first area of research was the design and implementation of low-power communication sub-systems that includes a AE-ADC converter and MAC routing protocol for these sensor nodes, employing techniques such as hardwired algorithms, lowered supply voltages, clock gating and subsystem shutdown. Prototypes were built on both an ASIC platform, in order to verify functionality and characterize power consumption. The resulting 0.13 mum silicon fabricated in Infineon's process was operational for supply voltages ranging from 1.0V to 1.5V, with power consumption of ~0.416mW that is the lowest solution for robust WBASN. The second area of research was the investigation of using LDPC codes error control method for WBASN application although their principal use to date has been in the DVB-S2 systems as the best option for the Forward Error Control (FEC). Techniques for improving the LDPC decoding algorithm were investigated, and method for reducing computational and hardware implementation complexity were evaluated