Managing Dynamic Partial Reconfiguration on Actual Heterogeneous Platform

This paper deals with partial reconfiguration issues on heterogeneous prototyping platforms (DSP/ FPGA). An analysis of multi-standard physical layer applications in terms of reconfiguration needs permits to extract several use cases of reconfiguration in a multi-standard handset: standard switching, mode switching, bug fixing, etc. The main difference between these schemes of reconfiguration is the level of granularity of the reconfiguration. We argue that a configuration manager needs to handle this multi-granularity of reconfiguration to optimize the change of context (either reconfigurable hardware or programmable software processing components) in terms of size of code, time to reconfigure, etc. The analysis also helps to determine the accurate level of flexibility needed through the reconfigurable architecture at different scales. Within this framework partial reconfiguration is an essential feature for optimizing the reconfiguration inside FPGA. We aim indeed at providing reconfiguration adequacy between re-configurability capabilities of hardware resources and reconfiguration needs of Software Defined Radio applications. Architectural solutions are proposed to implement partial reconfiguration on existing hardware combining DSP and FPGA