Unified verification environment for digital part of automotive mixed-signal integrated circuits

This thesis is concerned with unified verification environment for the verification of small designs of the digital part of integrated circuits with mixed signals. By unified verification environment is meant an environment suitable for both simulation and emulation. The first chapter describes the current verification methods of such designs. The second chapter presents the requirements that emulation places on the verification environment implemented according to the Universal Verification Methodology (UVM) and the attached implementation of proposed environment. The third chapter contains practical knowledge gained during the implementation of the unified verification environment, problems and their solutions, as well as several comparisons between simulation and emulation