HARDWARE IMPLEMENTATION OF NAVIGATION FILTERS FOR AUTOMATION OF DYNAMICAL SYSTEMS

To realize the full potential of autonomous navigation, computing at the edge of network infrastructure is critical in reducing response times. In navigation systems, high-performance computing resources are often necessary for state estimation. A hardware-focused approach using Field Programmable Gate Array (FPGA) for embedded design is presented to carry out high-performance edge computing required for advanced navigation of aerospace vehicles. FPGA architectures relieve the burden of storage-cum-processing of the measurement data while presenting a cost-optimized and accelerated infrastructure for navigation filter implementations. Leveraging the utility of software programming tools and the performance of customized hardware architecture, an FPGA-based hardware/software (HW/SW) codesign means for navigation filters is studied. The codesign splits a filter algorithm into tasks to be executed by the software and the hardware platforms. Transcendental function evaluations involved in a filter algorithm are tasked for software execution while a hardware platform implements the filter-specific logic at high speed. Three different navigation filter algorithms for embedded system design are implemented in this thesis: (a) Moving average filter for single-degree-of-freedom acceleration estimation, (b) Optimal Linear Translation and Attitude Estimator (OLTAE) for six-degrees-of-freedom pose estimation, and (c) Interferometric Vision-Based Navigation (iVisNav) for six-degrees-of-freedom relative motion rate estimation. The results of these hardware-based filter implementations demonstrate the capabilities of a custom embedded system design in a high-performance computational environment. The challenges involved in scientific computations using corresponding FPGA implementations of filter algorithms are analyzed and presented