Hardware resources contention-aware scheduling of hard real-time multiprocessor systems

[EN] In hard real-time embedded systems, switching to multicores is a step that most application domains delay asmuch as possible. This is mainly due to the number of sources of indeterminism, which mainly involve sharedhardware resources, such as buses, caches, and memories. In this paper, a new task model that considersthe interference that task execution causes in other tasks running on other cores due to memory contentionis proposed. We propose a scheduling algorithm that calculates the exact interference. We also analyse andcompare existing partitioning algorithms and propose three strategies to allocate tasks to cores to schedule asmany tasks as possible and minimise total interference.This work was supported by the Spanish Science and Innovation Ministry (predictable and dependable computer systems for Industry 4.0) under Grant MICINN: CICYT project PRECON-I4 and Grant TIN2017-86520-C3-1-RAceituno-Peinado, JM.; Guasque Ortega, A.; Balbastre, P.; Simó Ten, JE.; Crespo, A. (2021). Hardware resources contention-aware scheduling of hard real-time multiprocessor systems. Journal of Systems Architecture. 118:1-11. https://doi.org/10.1016/j.sysarc.2021.10222311111