Improvement of The ADC Resolution Based on FPGA Implementation of Interpolating Algorithm

International audienceThis paper exposes a method that gives us the possibility to use a low accuracy Analog-to-Digital Converter (ADC) in high-resolution measurements. We increase the resolution of a 12-bits ADC to 16-bits by adding samples which are calculated using Shannon interpolate algorithm. Thus, the digital signal has high resolution compared to measurements. Specific hardware architecture was developed to implement the algorithm in FPGA. The great advantages of the proposed design are an enhancement of ADC resolution and the continuous time is modeled as a white noise which is generated by the FPGA itself, obviating the need of an external noise source. Results were presented in order to confirm the metho