Junction temperature estimation approach based on TSEPs in multichip IGBT modules

Power semiconductor chips are parallelly packed in modules to achieve a specific current capacity and power level. An inhomogeneous degradation of the solder layer makes the junction temperature between chips unevenly distributed in multichip modules. The real matters of the junction temperature represented by the terminal electrical characteristics are not known when a junction temperature difference occurs in the internal chip of a multichip IGBT module. This paper analyzes the electrothermal coupling characteristics among the chips in multichip modules and establishes a mathematical model of the electrothermal relationship. To accurately control the different temperature distributions and uneven aging conditions of paralleled chips, two power modules or two discrete devices packaged in a TO-247 are connected in parallel to simulate a multichip power module. The correctness of the proposed electrothermal model and the feasibility of simulating multichip modules are verified through experiments. The findings indicate that the temperature evaluated by the threshold voltage approaches the maximum temperature of the chips inside the module. The junction temperature evaluated by the maximum change rate of the collector–emitter voltage and that of the collector current approach are used to obtain the average temperature