FPGA memory optimization for real-time imaging

International audiencemost of advanced driver assistance systems are developed for safety and better driving. Safety system using image processing, like Hough transform, requires a lot of memory whose underutilization can lead to decrease the real time performances. Internal memories on reconfigurable devices such as FPGA are limited in size, number and bandwidth. Memory optimization cannot be done solely at the application level. Holistic design-space exploration is necessary to leverage the inherent locality of applications and reduce memory accesses. In this paper, we target FPGA internal memories optimization by adding a small register-based multi-ported cache memory in front of each internal FPGA memory block to increase their bandwidth. The dimensions of this cache are explored according to the locality of the function implemented. The exploration uses a cumulative-write cache exhibiting 1.5 to 2 speedup compared to the best FPGA implementations. The solution is optimized with an identical number of memory and few added registers and LUT