BiCMOS circuit optimisation

This thesis is concerned with optimising BiCMOS circuits. A numerical optimiser finds the set of arguments to a cost function that results in its minimum value. The arguments are the component values of a circuit, and the result of the optimisation is a circuit whose design cannot be improved without changing its topology.In the first part of this thesis, the numerical optimiser individually adjusts the size of each stage in a CMOS buffer. It produces buffers that either are the fastest possible, the fastest for a given silicon area, or occupy the minimum silicon area for a given delay. When optimising silicon area for a given delay, an area saving of typically 3.5% is obtained compared with the best existing designs. When optimising delay for a given silicon area, the saving is typically 2.5%.The second part of this thesis describes a numerical optimiser linked to the SPICE circuit simulator. This 'numerical circuit optimiser' takes a SPICE-like input net list and optimises component values in the circuit. As an example, the transistor sizes in standard BiCMOS buffers are optimised and compared with those produced using analytical BiCMOS delay expressions taken from the literature. The numerical optimiser always produced buffers with the lowest delays.The final part of this thesis addresses the problem of operating BiCMOS buffers at reduced supply voltages. Low voltage BiCMOS buffer designs taken from the literature 43, 44, 47, 53, 54 are numerically optimised to allow a fair comparison of their performance. A new 'bootstrap BiCMOS buffer' that combines temporary saturation and a bootstrap capacitor is presented. Simulations show the new bootstrap BiCMOS buffer is faster than the best existing BiCMOS designs and faster than CMOS designs down to a supply voltage of 1.5V. Ring oscillators, realised on a foundry BiCMOS process, show that the new bootstrap BiCMOS buffer is faster than all other BiCMOS designs. It was also faster than CMOS designs down to a supply voltage of 1.9V.