Testing analogue circuits : design for testability structures and an investigation into supply current monitoring

The increasing use of analogue and mixed-signal systems makes it necessary to consider Design For Testability (DFT). Together with the 1EEE P1149.4 Standard Working Group, this research proposes a testability structure to facilitate the testing of analogue circuits (included in a mixed-signal system) at all levels, from chip to board or system. At this early stage, the work has concentrated on identifying the fundamental requirements for the structure. The starting point was to develop a DFT structure for analogue interconnect testing at board level without using physical probes, which is the most urgent facility needed by the design and test community. The study confirmed that the testing process has to be able to verify not only the integrity of the chip interconnections, but also the values of the intervening discrete components. Based on this confirmation, a conceptual DFT structure that supports these requirements has been proposed. The main element of the structure is known as Analogue Boundary Cell (ABC). It has been demonstrated that the structure is fully compatible with the 1EEE 1149.1 Test access Port (TAP) control protocol. An extension to this structure has also been developed to provide test access to the analogue circuits in the chip. Several structures have been proposed and all of them can be operated by the 1EEE 1149.1 TAP Controller. At the same time, based on the assumptions that analogue circuits are made from modules as in ASIC approach, and access to be provided is expected at each module boundary, an investigation to find the fundamental requirements of reliable test procedures for modules that are involved in analogue signal processing has been carried out. In the absence of any general analogue fault model, the work has concentrated on analysing the behaviour of selected primitive analogue and mixed-signal modules under catastophic fault conditions.