In this paper, we present a functional description of a VLSI chip aimed at reducing the cost of data transmission and data access within information processing machines and distributed information systems. The chip maps standard character codes (e.g., ASCII) into more efficient codes (e.g., Huffman\u27s codes) using a tree module of basic cells. In bit-serial communication controllers, for example, the parallel-to-serial transformation unit can be simply replaced by the proposed chip. The VLSI design can provide speeds that far exceed current and projected peak transfer rates of high-speed disks and communication controllers
In this paper, we propose a modified Manchester and Miller encoder that can operate in high frequenc...
An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is present...
Data compression methods are used to reduce the redundancy in data representation in order to decrea...
In this paper, we propose a new class of VLSI architectures for data transformation of tree-based co...
In this paper, we describe the architecture and design of a CMOS VLSI chip for data compression and ...
Using VLSI technology, it will soon be possible to implement entire computing systems on one monolit...
Data compression is the reduction of redundancy in data representation in order to decrease storage ...
A new class of VLSI architectures for data transformation of tree-based codes is proposed. The focus...
A bidirectional serial link on-chip implementation is going to be assessed so as to set the option o...
Using VLSI technology, it will soon be possible to implement entire computing systems on one monolit...
A compression algorithm that is tailored to utilize the enormous speed and memory size of supercompu...
The performance of many digital systems today is limited by the interconnection bandwidth between ch...
The process of Integrated Circuits (IC) started its era of VLSI (Very Large Scale Integration) in 19...
In this paper, we propose a modified Manchester and Miller encoder that can operate in high frequenc...
An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is present...
Data compression methods are used to reduce the redundancy in data representation in order to decrea...
In this paper, we propose a new class of VLSI architectures for data transformation of tree-based co...
In this paper, we describe the architecture and design of a CMOS VLSI chip for data compression and ...
Using VLSI technology, it will soon be possible to implement entire computing systems on one monolit...
Data compression is the reduction of redundancy in data representation in order to decrease storage ...
A new class of VLSI architectures for data transformation of tree-based codes is proposed. The focus...
A bidirectional serial link on-chip implementation is going to be assessed so as to set the option o...
Using VLSI technology, it will soon be possible to implement entire computing systems on one monolit...
A compression algorithm that is tailored to utilize the enormous speed and memory size of supercompu...
The performance of many digital systems today is limited by the interconnection bandwidth between ch...
The process of Integrated Circuits (IC) started its era of VLSI (Very Large Scale Integration) in 19...
In this paper, we propose a modified Manchester and Miller encoder that can operate in high frequenc...
An asynchronous VLSI implementation of the International Data Encryption Algorithm (IDEA) is present...
Data compression methods are used to reduce the redundancy in data representation in order to decrea...