Performance Evaluation Of 3D-Interconnect Architectures For Network Line Cards

In this paper, we propose two off-chip interconnect architectures, called 3D-interconnects, to communicate between processing elements and memory modules located on network line cards. The goal of the 3D-interconnect architectures is to increase the throughput of the memory system since most currently deployed line card designs reach their maximum transfer rate. Moreover, line rates are constantly increasing while at the same time more data and functionality are embedded in each packet. The 3D-interconnect architectures allow multiple packet processing elements on a line card to access multiple memory modules. The novelty of the proposed interconnects is their application and implementation as off-chip interconnects on the line card board. Our interconnects includes multiple, highly efficient techniques to route, switch, and control packet flows in order to minimize congestion spots within the interconnects and packet loss. Performance results show that both interconnect designs achieve high throughput, low latency results surpassing other common interconnects currently deployed. Moreover, the interconnects were able to sustain high traffic load while keeping low failure rates and high bandwidth utilization levels