Add to ORKGThe impact of process defects on ECL power-delay product has been evaluated. The authors have developed the modeling equations including the process defects in the delay analysis. The delay equation provides the insight into the sensitivity of various process defects in ECL gate delay. The testing model equations are physics based and can be generalized to digital circuits other than ECL logic
Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, lik...
Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, lik...
MO- WORK REPOmD on delay testing is applicable only to the scan type of circuits. This restricted pr...
The impact of process defects on the emitter-coupled-logic (ECL) power-delay product has been evalua...
The impact of process defects on the emitter-coupled-logic (ECL) power-delay product has been evalua...
Soft errors can occur in digital integrated circuits (ICs) as a result of an electromagnetic disturb...
Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, suc...
As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defe...
[[abstract]]The problem of diagnosing delay defects is defined using a statistical timing model. The...
The increasing clock frequencies have led to new fault effects of production defects. These so calle...
[[abstract]]This paper defines a new diagnosis problem for diagnosing delay defects based upon stati...
[[abstract]]The performance of deep submicron designs can be affected by various parametric variatio...
Technology scaling and manufacturing process affect the performance of digital circuits, making them...
108 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2003.We use circuit delay bounding...
An accurate delay model has been developed and integrated in a delay-fault test-pattern generator. T...
Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, lik...
Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, lik...
MO- WORK REPOmD on delay testing is applicable only to the scan type of circuits. This restricted pr...
The impact of process defects on the emitter-coupled-logic (ECL) power-delay product has been evalua...
The impact of process defects on the emitter-coupled-logic (ECL) power-delay product has been evalua...
Soft errors can occur in digital integrated circuits (ICs) as a result of an electromagnetic disturb...
Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, suc...
As technology scales down, digital VLSI circuits are prone to many manufacturing defects. These defe...
[[abstract]]The problem of diagnosing delay defects is defined using a statistical timing model. The...
The increasing clock frequencies have led to new fault effects of production defects. These so calle...
[[abstract]]This paper defines a new diagnosis problem for diagnosing delay defects based upon stati...
[[abstract]]The performance of deep submicron designs can be affected by various parametric variatio...
Technology scaling and manufacturing process affect the performance of digital circuits, making them...
108 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 2003.We use circuit delay bounding...
An accurate delay model has been developed and integrated in a delay-fault test-pattern generator. T...
Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, lik...
Integrated circuits (ICs) sometimes fail when their power supply is disrupted by external noise, lik...
MO- WORK REPOmD on delay testing is applicable only to the scan type of circuits. This restricted pr...