Marvle: A Vlsi Chip For Data Compression Using Tree-Based Codes

In this paper, we describe the architecture and design of a CMOS VLSI chip for data compression and decompression using tree-based codes. The chip, called MARVLE, implements a Memory-based ARchitecture for Variable Length Encoding and decoding based on tree-based codes. The architecture is based on an efficient scheme of mapping the tree representing any binary code onto a memory device. A prototype 2-μm CMOS VLSI chip has been designed, verified and fabricated by MOSIS facility. The chip has a 512 x 12 static RAM with an access time of 4 ns and logic circuitry for compression as well as decompression. The chip occupies a silicon area of 6.8 x 6.9 mm2 and consists of 49 695 transistors. The prototype chip yields a compression rate of 95.2 Mbits/s and a decompression rate of 60.6 Mbits/s with a clock rate of 83.3 MHz. The VLSI hardware can be used to implement the JPEG baseline compression scheme. © 1993 IEE