High-Performance CMOS Front-End ASICs for SiPM Detectors and High-Frequency Ultrasound and Photoacoustic Imaging

Silicon photomultiplier (SiPM), as a high sensitivity photon detector, has been widely used in high energy physics, positron emission tomography imaging, and light detection and ranging applications. The slow-rising edge of standard SiPM signal, however, makes the timing measurement sensitive to noise and leads to poor timing resolution. Besides, the SiPM energy measurement utilizing charge-sensitive amplifiers suffers from high power consumption and is not suitable for array-based SiPM readout systems. To solve these issues, two hardware prototypes in a 180 nm CMOS process have been fabricated and experimentally characterized. The first prototype is a single-channel SiPM readout featuring an on-chip fast signal generator and a customized successive-approximation-register (SAR) analog-to-digital converter (ADC). The on-chip fast-signal generator sharpens the slow-rising edge of SiPM signal improving the timing resolution. The customized ADC uses the SiPM charge integrator as the ADC track-and-hold circuit lowering the ADC power consumption. Measurement results show the readout front-end achieves a timing resolution of 151 ps, while dissipating 4.02 mW of power. The second prototype demonstrates a shared SAR ADC architecture in multi-channel SiPM readout to reduce the chip area and power consumption. The ADC is shared by 16 readout channels in a time-multiplexed manner, and achieves an SFDR of 58.34 dB and an SNDR of 51.37 dB at 16 MS/s. High-frequency (30 to 100 MHz) ultrasound and photoacoustic imaging with improved microscopic resolution opens new medical applications in ophthalmology, intravascular imaging and systemic sclerosis. To break the tradeoff between noise and wideband impedance matching, a wideband low-noise amplifier (LNA) with noise and distortion cancellation is developed. The LNA employs a resistive shunt-feedback structure with feedforward noise-canceling technique to accomplish both wideband impedance matching and low-noise performance. A complementary CMOS topology is also developed to cancel the second-order harmonic distortion and enhance the linearity. A front-end including the proposed LNA and a variable gain amplifier is designed and fabricated in a 180 nm CMOS process. At 80 MHz, the front-end achieves an input-referred noise density of 1.36 nV/sqrt(Hz), an S11 better than -16 dB, and a total harmonic distortion of -55 dBc while consuming 37 mW of power.Electrical and Computer Engineering, Department o