Add to ORKGInternational audienceThe single event upset (SEU) tolerance of various latch designs in 0.13um CMOS technology has been studied by both measurement and simulation. The aim of this work is to optimize the design for critical registers on the next generation pixel readout chip for ATLAS upgrades (denominated FE-I4). Results form irradiations with 24 GeV protons will be presented and compared to previous values obtained with heavy ions. Layout effects will be discussed and quantified along with other design consideration
International audienceEffects of Single Event Upsets (SEU) and Single Event Transients (SET) are stu...
The radiation tolerance of a commercial 0.13 mu m CMOS technology is investigated. Total ionizing do...
We have studied single event effects in static and dynamic registers designed in a quarter micron CM...
International audienceThe single event upset (SEU) tolerance of various latch designs in 0.13um CMOS...
The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, config...
International audienceThe FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. F...
International audienceThe RD53 collaboration was established to develop the next generation of pixel...
We present a method of estimating the sensitivity to radiation- induced Single Event Upset (SEU) in ...
Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A ...
International audienceA novel memory structure, designed to tolerate SEU perturbations, has been imp...
International audienceIndividual transistors, resistors and shift registers have been designed using...
A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Had...
We report on several irradiation studies performed on BTeV preFPIX2 pixel readout chip prototypes ex...
Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. Hig...
In future experiments the readout electronics for pixel detectors is required to be resistant to a v...
International audienceEffects of Single Event Upsets (SEU) and Single Event Transients (SET) are stu...
The radiation tolerance of a commercial 0.13 mu m CMOS technology is investigated. Total ionizing do...
We have studied single event effects in static and dynamic registers designed in a quarter micron CM...
International audienceThe single event upset (SEU) tolerance of various latch designs in 0.13um CMOS...
The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, config...
International audienceThe FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. F...
International audienceThe RD53 collaboration was established to develop the next generation of pixel...
We present a method of estimating the sensitivity to radiation- induced Single Event Upset (SEU) in ...
Radiation from terrestrial and space environments is a great danger to integrated circuits (ICs). A ...
International audienceA novel memory structure, designed to tolerate SEU perturbations, has been imp...
International audienceIndividual transistors, resistors and shift registers have been designed using...
A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Had...
We report on several irradiation studies performed on BTeV preFPIX2 pixel readout chip prototypes ex...
Integrated Circuits in space suffer from reliability problems due to the radiative surroundings. Hig...
In future experiments the readout electronics for pixel detectors is required to be resistant to a v...
International audienceEffects of Single Event Upsets (SEU) and Single Event Transients (SET) are stu...
The radiation tolerance of a commercial 0.13 mu m CMOS technology is investigated. Total ionizing do...
We have studied single event effects in static and dynamic registers designed in a quarter micron CM...