Direct Digital Synthesis Optimization Based on VHDL Code

In this paper, we will describe the synthesis of Direct Digital Synthesis (DDS) circuit using VHDL language. Nowadays the DDS are being used widely in the fields of telecommunication and especially as generators. The DDS circuits are used to generate analog signals with the use of fully digital circuits. The aim of this work is to present the implementation of DDS with the VHDL language, which offers compatibility with FPGA devices. Initially, the VHDL code was generated automatically via Matlab / Simulink model, designed by using HDL Coder components which are compatible with VHDL. Finally, in order to optimize the automatically generated code and the performance of the DDS circuit, the VHDL code is modified. Due to this optimization done on VHDL code about 10% improvement in power consumption and reduction of resource utilization is achieved