Experimental analysis and circuit model of an inductive type high temperature superconducting fault current limiter

A basic inductive type high temperature superconducting fault current limiter prototype has been built and tested at the Department of Electrical Engineering of the University of Tokyo. The experimental static V-I characteristics shows a change in the impedance of the device when its limiting current is reached. A circuit model of the fault current limiter is developed by means of a non linear inductor with memory. A good agreement is obtained between numerical and experimental V-I characteristics. Dynamic characteristics are numerically studied by means of the circuit model