Add to ORKGInternational audienceThis paper presents some work in progress on the design and implementation of efficient floating-point software support for embedded integer processors. We provide quantitative evidence of the benefits of supporting various non-generic (that is, specialized, fused, or simultaneous) operations in addition to the five basic arithmetic operations: for individual calls, speedups range from 1.12 to 4.86, while on DSP kernels and benchmarks, our approach allows us to be up to 1.34x faster
Hybrid floating-point (FP) implementations improve software FP performance without incurring the are...
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
We see that in most computers and applications the CPU is taxed, first and foremost, before other pi...
International audienceThis paper presents some work in progress on the design and implementation of ...
We disclose hardware (HW) intrinsic CPU or DSP instructions architecture and microarchitecture that ...
It has been shown that FPGAs could outperform high-end microprocessors on floating-point computation...
International audienceThis paper presents some work in progress on fast and accurate floating-point ...
Compulsory normalization of the represented numbers is a key requirement of the floating-point stand...
ECTI TRANSACTIONS ON COMPUTER AND INFORMATION TECHNOLOGY, VOL.6, NO.1 May 2012This paper presents th...
Many scenarios demand a high processing power often combined with a limited energy budget. A way to ...
This paper describes an open-source and highly scalable floating-point unit (FPU) for embedded syste...
An effective approach to handling the theory of floating-point is to reduce it to the theory of bit-...
Floating-point numbers are broadly received in numerous applications due their element representatio...
We present a methodology for generating floating-point arithmetic hardware designs which are, for su...
Floating-point computations are at the heart of much of the computing done in high energy physics. ...
Hybrid floating-point (FP) implementations improve software FP performance without incurring the are...
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
We see that in most computers and applications the CPU is taxed, first and foremost, before other pi...
International audienceThis paper presents some work in progress on the design and implementation of ...
We disclose hardware (HW) intrinsic CPU or DSP instructions architecture and microarchitecture that ...
It has been shown that FPGAs could outperform high-end microprocessors on floating-point computation...
International audienceThis paper presents some work in progress on fast and accurate floating-point ...
Compulsory normalization of the represented numbers is a key requirement of the floating-point stand...
ECTI TRANSACTIONS ON COMPUTER AND INFORMATION TECHNOLOGY, VOL.6, NO.1 May 2012This paper presents th...
Many scenarios demand a high processing power often combined with a limited energy budget. A way to ...
This paper describes an open-source and highly scalable floating-point unit (FPU) for embedded syste...
An effective approach to handling the theory of floating-point is to reduce it to the theory of bit-...
Floating-point numbers are broadly received in numerous applications due their element representatio...
We present a methodology for generating floating-point arithmetic hardware designs which are, for su...
Floating-point computations are at the heart of much of the computing done in high energy physics. ...
Hybrid floating-point (FP) implementations improve software FP performance without incurring the are...
Thesis (M.Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer...
We see that in most computers and applications the CPU is taxed, first and foremost, before other pi...