Novel Synthesis Methodology in Digital IC Design and Automation to Reduce NRE costs and Time-to-Market

The number of incremental and iterative steps in the digital IC design & automation methodology will decide the non-recurring-engineering (NRE) costs and time-to-market (TTM). Since the aforementioned factors are the major driving factors of the IC design industry, many algorithms were proposed in the last few decades to minimize/optimize the number of design steps in the conventional digital IC design & automation methodology. However, the conventional front end and back end designs have been carried out separately, which has limited the further minimization of design steps. Here we propose a novel digital IC design & automation methodology, which reduces the NRE costs and TTM by merging the front end and back end designs partially. It maps the input RTL description directly to their corresponding physical layouts(derived using the existing CAD tools and stored in a pre-computed library) without going through the all the steps in conventional logic and \ud physical synthesis process. As part of the proposed methodology, we use a pre-computed library which stores all required physical layouts and their Boolean functions. We have exploited the functional symmetry and negation-permutation-negation (NPN) class representations to decoct the library size and number of comparisons. The functional\ud symmetry reduced the number of required pre-computed circuits in our experiments from ] 1031 to 222 (464.4% reduction in the memory size) and helps in maintaining the regularity in the design, which is a major concern for engineering change order