Existing semantic formalisations of the Intel-x86 architecture cover only a small fragment of its available features that are relevant for the consistency semantics of multi-threaded programs as well as the persistency semantics of programs interfacing with non-volatile memory. We extend these formalisations to cover: (1) non-temporal writes, which provide higher performance and are used to ensure that updates are flushed to memory; (2) reads and writes to other Intel-x86 memory types, namely uncacheable, write-combined, and write-through; as well as (3) the interaction between these features. We develop our formal model in both operational and declarative styles, and prove that the two characterisations are equivalent. We have empirically ...
International audienceConcurrent programs running on weak memory models exhibit re-laxed behaviours,...
Parallel systems that support the shared memory abstraction are becoming widely accepted in many are...
Shared memory concurrency relies on synchronisation primitives: compare-and-swap, load-reserve/store...
International audienceExisting semantic formalisations of the Intel-x86 architecture cover only a sm...
Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance...
Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance...
Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance...
Multiprocessors are now dominant, but real multiprocessors do not provide the sequentially consisten...
The advent of non-volatile memory (NVM) technologies is expected to transform how software systems a...
Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see it...
Heterogeneous CPU/FPGA devices, in which a CPU and an FPGA can execute together while sharing memory...
AbstractA programmer-centric model describes the memory consistency rules of amultiprocessor as a co...
The rise of persistent memory is disrupting computing to its core. Our work aims to help programmers...
The Total Store Order memory model is widely implemented by modern multicore architectures such as x...
Emerging non-volatile memory (NVM) technologies enable data persistence at the main memory level at ...
International audienceConcurrent programs running on weak memory models exhibit re-laxed behaviours,...
Parallel systems that support the shared memory abstraction are becoming widely accepted in many are...
Shared memory concurrency relies on synchronisation primitives: compare-and-swap, load-reserve/store...
International audienceExisting semantic formalisations of the Intel-x86 architecture cover only a sm...
Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance...
Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance...
Emerging non-volatile memory (NVM) technologies promise the durability of disks with the performance...
Multiprocessors are now dominant, but real multiprocessors do not provide the sequentially consisten...
The advent of non-volatile memory (NVM) technologies is expected to transform how software systems a...
Various memory consistency model implementations (e.g., x86, SPARC) willfully allow a core to see it...
Heterogeneous CPU/FPGA devices, in which a CPU and an FPGA can execute together while sharing memory...
AbstractA programmer-centric model describes the memory consistency rules of amultiprocessor as a co...
The rise of persistent memory is disrupting computing to its core. Our work aims to help programmers...
The Total Store Order memory model is widely implemented by modern multicore architectures such as x...
Emerging non-volatile memory (NVM) technologies enable data persistence at the main memory level at ...
International audienceConcurrent programs running on weak memory models exhibit re-laxed behaviours,...
Parallel systems that support the shared memory abstraction are becoming widely accepted in many are...
Shared memory concurrency relies on synchronisation primitives: compare-and-swap, load-reserve/store...