High-level tools and methods for electron-beam debug and failure analysis of integrated circuits

A current research project at IMAG/TIM3 Laboratory aims at developing an integrated test system combining the use of the scanning electron microscope (SEM), used in the voltage contrast mode, with a new high-level approach fault location in complex VLSI circuits, in order to obtain a completely automated diagnosis process. The two research themes of this project are: prototype validation of known circuits, on which CAD information is available, and failure analysis of unknown circuits, which are compared to reference circuits. For prototype validation, a knowledge-based approach to fault location is used. Concerning failure analysis, automatic image comparison based on pattern recognition techniques is performed. The authors present these two methodologies, focusing on the SEM-based data acquisition process