Architecture experimentation with the SYCO silicon compiler is described. It is noted that, although SYCO starts from a behavioral description, the translation scheme (from algorithmic description to layout) is easy to understand and there is a correspondence between the input description and the layout. The designer can easily modify the input description in order to force the compiler to produce a given result. SYCO provides a tool called ARTS that helps the user to make architectural tradeoffs. ARTS provides commands that modify automatically the input description in order to obtain a new architectural solution without modifying the function of the circuit. An example of architecture experimentation is given
Design of array processors needs suited CAD tools for each design phase, from behavioral description...
The analysis of an architecture may provide statistic information on the use of the resources and on...
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a hi...
International audienceThe principles of SYCO are explained and its characteristics compared with tho...
The SYCO system is a silicon compiler for VLSI ASICs specified by algorithms. SYCO starts from an al...
ISBN: 9024735610The SYCO system is a silicon compiler for VLSI ASICs specified by algorithms. The SY...
Silicon compilation is a term used for many different purposes. In this paper we define silicon comp...
With increasing complexity of modern embedded systems, the availability of highly optimizing compile...
This paper considers the role of performance and area esti-mates from behavioral synthesis in design...
We describe EXPRESSION, a language supporting architectural design space exploration for embedded Sy...
We have been developing a Compiler Generator which makes a system designer evaluate his/her architec...
The AMICAL architectural synthesis system starts with a behavioral specification given in VHDL, perf...
International audienceThis paper presents the method developed in the architecture compiler SCOOP: h...
The utilization of application specific instruction-set processors (ASIPs) allows for realizing Syst...
International audienceSysADL is a SysML profile for describing architectures using the well-known an...
Design of array processors needs suited CAD tools for each design phase, from behavioral description...
The analysis of an architecture may provide statistic information on the use of the resources and on...
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a hi...
International audienceThe principles of SYCO are explained and its characteristics compared with tho...
The SYCO system is a silicon compiler for VLSI ASICs specified by algorithms. SYCO starts from an al...
ISBN: 9024735610The SYCO system is a silicon compiler for VLSI ASICs specified by algorithms. The SY...
Silicon compilation is a term used for many different purposes. In this paper we define silicon comp...
With increasing complexity of modern embedded systems, the availability of highly optimizing compile...
This paper considers the role of performance and area esti-mates from behavioral synthesis in design...
We describe EXPRESSION, a language supporting architectural design space exploration for embedded Sy...
We have been developing a Compiler Generator which makes a system designer evaluate his/her architec...
The AMICAL architectural synthesis system starts with a behavioral specification given in VHDL, perf...
International audienceThis paper presents the method developed in the architecture compiler SCOOP: h...
The utilization of application specific instruction-set processors (ASIPs) allows for realizing Syst...
International audienceSysADL is a SysML profile for describing architectures using the well-known an...
Design of array processors needs suited CAD tools for each design phase, from behavioral description...
The analysis of an architecture may provide statistic information on the use of the resources and on...
The rapid growth of silicon densities has made it feasible to deploy reconfigurable hardware as a hi...