Automatic VHDL-C Interface Generation for Distributed Cosimulation: Application to Large Design Examples

For functional validation of heterogeneous embedded systems, hardware/software (Hw/Sw) cosimulation methodology is mandatory. This paper deals with a distributed cosimulation environment for heterogeneous systems prototyping. The cosimulation environment allows handling all kinds of distributed architectures regardless the communication scheme used, cosimulation at different levels of abstraction and smooth transition to the cosynthesis process. The approach can handle any number of hardware modules, software modules, and debugging tools, which can be used simultaneously. This flexibility is obtained thanks to an automatic cosimulation interface generation tool, which creates links between Hw and Sw simulation environments. The resulting environment is very easy to use and our cosimulation model has been validated on very large industrial examples. The experiments show that VHDL-C cosimulation is faster than classical simulation approaches