In this paper, two low-cost solutions devoted to provide processor-based systems with error-detection capabilities are compared. The effects of single event upsets (SEUs) and single event transients (SETs) are studied through simulation-based fault injection. The error-detection capabilities of a hardware-implemented solution based on parity code are compared with those of a software-implemented solution based on source-level code modification. Radiation testing experiments confirmed results obtained by simulation
Modern processors embed features such as pipelined execution units and cache memories that can hardl...
The effects of transient bit flips on the operation of processor based architectures is investigated...
4noBit-flips caused by single-event upsets (SEUs) are a well-known problem in computer memories. A S...
International audienceIn this paper two lost-cost solutions for providing error detection capabiliti...
In this paper are first summarized representative examples of anomalies observed in systems operatin...
International audienceThis paper presents a new fault injection method based on the CEU (Code Emulat...
International audienceSingle Event Upset (SEU) phenomena is becoming a major concern in applications...
This paper presents a detailed analysis of the efficiency of software-based techniques to mitigate S...
International audienceIn this paper, proposed software tools for predicting the rate and nature of o...
International audienceThis paper describes two different but complementary approaches that can be us...
Abstract—An approach to study the effects of single event upsets (SEU) by fault injection performed ...
International audienceIn this paper is described a purely software technique allowing to detect SEUs...
International audienceIn this paper, a new methodology for the injection of single event upsets (SEU...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0018-9499International audienceAn ...
The project successfully demonstrated that dual lock-step comparison of commercial RISC processors i...
Modern processors embed features such as pipelined execution units and cache memories that can hardl...
The effects of transient bit flips on the operation of processor based architectures is investigated...
4noBit-flips caused by single-event upsets (SEUs) are a well-known problem in computer memories. A S...
International audienceIn this paper two lost-cost solutions for providing error detection capabiliti...
In this paper are first summarized representative examples of anomalies observed in systems operatin...
International audienceThis paper presents a new fault injection method based on the CEU (Code Emulat...
International audienceSingle Event Upset (SEU) phenomena is becoming a major concern in applications...
This paper presents a detailed analysis of the efficiency of software-based techniques to mitigate S...
International audienceIn this paper, proposed software tools for predicting the rate and nature of o...
International audienceThis paper describes two different but complementary approaches that can be us...
Abstract—An approach to study the effects of single event upsets (SEU) by fault injection performed ...
International audienceIn this paper is described a purely software technique allowing to detect SEUs...
International audienceIn this paper, a new methodology for the injection of single event upsets (SEU...
INTERNATIONAL STANDARD SERIAL NUMBERS (Translation and Original): 0018-9499International audienceAn ...
The project successfully demonstrated that dual lock-step comparison of commercial RISC processors i...
Modern processors embed features such as pipelined execution units and cache memories that can hardl...
The effects of transient bit flips on the operation of processor based architectures is investigated...
4noBit-flips caused by single-event upsets (SEUs) are a well-known problem in computer memories. A S...