Modeling and design of asynchronous priority arbiters for on-chip communication systems

International audienceThis paper addresses the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studied in the perspective of making easier and more practical the design of future GALS or GALA SoCs. The paper focuses on high-level modeling and delay-insensitive implementations of fixed and dynamic priority arbiter. Pre-layout simulations show that arbiters which are able to process several hundreds mega requests per second can be designed using the 0.18 mu m CMOS process of STMicroelectronics