Deals with CPC, the SYCO control section synthesizer. CPC receives a hierarchical high level description of the circuit to be designed. The control section generated by CPC is made up of a stack of control slices. Each one is implemented by a single PLA. For each control slice, CPC performs three steps: (1) state table generation, (2) logic optimization and the completion of implicit jumps, (3) PLA generation. The author shows how the synthesis scheme can depend on the synthesizer intermediate form and the target architecture of the controller generated. The advantage of the CPC, compared to other control section synthesizers, is that the intermediate form is kept in a high level language. And it is well adapted to the target architecture
In this paper we discuss the generation of reprogrammable controllers. This generation is performed ...
We investigate a two-level hierarchical architecture for hybrid control. On the top, a discrete supe...
A controller synthesizer, tha t is part of a design sys-tem by which algorithms unsuitable for stand...
ISBN: 0818608722The authors describe a design-for-testability strategy for the SYCO control section ...
This paper considers the problem of control synthesis for a class of discrete event systems composed...
The Continuous Process Control package (CPC) is one of the components of the CERN Unified Industrial...
A method is presented for the synthesis of the microarchitecture of controlpaths. This method is cal...
Deals with a design for testability strategy for the SYCO control section compiler developed in the ...
Existing techniques in high-level synthesis mostly assume a simple controller architecture model in ...
This paper describes a new high-level synthesis system based on the hierarchical Production-Based Sp...
The SYCO system is a silicon compiler for VLSI ASICs specified by algorithms. SYCO starts from an al...
Abstract—Creating parameterized “chip generators ” has been proposed as one way to decrease chip NRE...
The article concerns the problem of structure-and-parametric optimization of a cascade automatic con...
In modern day production, the ability to quickly implement a control system is of increasing importa...
The complexity of the circuit that can fit cm an integrated circuit (IC) chip has readied the level ...
In this paper we discuss the generation of reprogrammable controllers. This generation is performed ...
We investigate a two-level hierarchical architecture for hybrid control. On the top, a discrete supe...
A controller synthesizer, tha t is part of a design sys-tem by which algorithms unsuitable for stand...
ISBN: 0818608722The authors describe a design-for-testability strategy for the SYCO control section ...
This paper considers the problem of control synthesis for a class of discrete event systems composed...
The Continuous Process Control package (CPC) is one of the components of the CERN Unified Industrial...
A method is presented for the synthesis of the microarchitecture of controlpaths. This method is cal...
Deals with a design for testability strategy for the SYCO control section compiler developed in the ...
Existing techniques in high-level synthesis mostly assume a simple controller architecture model in ...
This paper describes a new high-level synthesis system based on the hierarchical Production-Based Sp...
The SYCO system is a silicon compiler for VLSI ASICs specified by algorithms. SYCO starts from an al...
Abstract—Creating parameterized “chip generators ” has been proposed as one way to decrease chip NRE...
The article concerns the problem of structure-and-parametric optimization of a cascade automatic con...
In modern day production, the ability to quickly implement a control system is of increasing importa...
The complexity of the circuit that can fit cm an integrated circuit (IC) chip has readied the level ...
In this paper we discuss the generation of reprogrammable controllers. This generation is performed ...
We investigate a two-level hierarchical architecture for hybrid control. On the top, a discrete supe...
A controller synthesizer, tha t is part of a design sys-tem by which algorithms unsuitable for stand...