ISBN: 0818607033The necessity to consider fault models representing real faults occurring in integrated circuits led recently to the definitions of low-level fault hypotheses such as transistors stuck-on, stuck-open, and cuts of metallization. It is then natural to base the design of self-checking systems on this type of fault hypotheses. General layout rules are derived for the design of strongly fault secure (SFS) NMOS circuits (i.e. for the largest class of circuits that achieve the totally self-checking goal). Those rules are derived in order to detect unidirectional errors, which have been recognized as a large category of errors appearing in integrated circuits. Examples of the application of these layout rules are given for the desig...
A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is pre...
[[abstract]]The authors present a novel approach to designing TSC (totally self-checking) CMOS circu...
Scaling of transistor's channel length is entering the realm of atomic and molecular geometries maki...
Deals with the design of self-checking NMOS circuits. Two types of test are planned for the use of t...
145 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1982.This research has mainly cent...
In this paper we propose signal coding and CMOS gates that are suitable to self-checking circuits wi...
In the area of self-checking circuit designs, it is known that no combinational totally self-checkin...
In this paper we propose signal coding and CMOS gates that are suitable to self-checking circuits wi...
A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for mu...
A CMOS gate structure tolerating all single transistor stuck-at faults and a large set of multiple f...
Thls thesis presents an algorithm for fault simulation of metal-oxide-semiconductor (MOS), field-eff...
ISBN: 0769506135IC technologies are approaching the ultimate limits of silicon in terms of device si...
Includes bibliographical references (leaf 24)The Project is based on the study of NanoMemory structu...
A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is pre...
The design of self-checking circuits through output encoding finds a bottleneck in the realization o...
A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is pre...
[[abstract]]The authors present a novel approach to designing TSC (totally self-checking) CMOS circu...
Scaling of transistor's channel length is entering the realm of atomic and molecular geometries maki...
Deals with the design of self-checking NMOS circuits. Two types of test are planned for the use of t...
145 p.Thesis (Ph.D.)--University of Illinois at Urbana-Champaign, 1982.This research has mainly cent...
In this paper we propose signal coding and CMOS gates that are suitable to self-checking circuits wi...
In the area of self-checking circuit designs, it is known that no combinational totally self-checkin...
In this paper we propose signal coding and CMOS gates that are suitable to self-checking circuits wi...
A technique for designing totally self-checking (TSC) FCMOS (Fully Complementary MOS) designs for mu...
A CMOS gate structure tolerating all single transistor stuck-at faults and a large set of multiple f...
Thls thesis presents an algorithm for fault simulation of metal-oxide-semiconductor (MOS), field-eff...
ISBN: 0769506135IC technologies are approaching the ultimate limits of silicon in terms of device si...
Includes bibliographical references (leaf 24)The Project is based on the study of NanoMemory structu...
A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is pre...
The design of self-checking circuits through output encoding finds a bottleneck in the realization o...
A strongly fault secure (SFS) ALU design based on the Berger check prediction (BCP) technique is pre...
[[abstract]]The authors present a novel approach to designing TSC (totally self-checking) CMOS circu...
Scaling of transistor's channel length is entering the realm of atomic and molecular geometries maki...