An efficient BICS design for SEUs detection and correction in semiconductor memories

Gill, B.
Nicolaidis, M.
Wolff, F.
Papachristou, C.
Garverick, S.

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Publication date

January 2005

DOI

10.1109/DATE.2005.54

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Abstract

ISBN: 0769522882We propose a new built-in current sensor (BICS) to detect single event upsets (SEUs) in SRAM. The BICS is designed and validated for 100 nm process technology. The BICS reliability analysis is provided for process, voltage and temperature variations, and power supply noise. The BICS detects various shapes of current pulses generated due to particle strike. The BICS power consumption and area overhead are also provided. The BICS is found to be very reliable for process, voltage and temperature variations and under stringent noise conditions

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An efficient BICS design for SEUs detection and correction in semiconductor memories

Abstract

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An efficient BICS design for SEUs detection and correction in semiconductor memories

Abstract

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