Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments

Calin, T.
Vargas, F.,
Nicolaidis, M.

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Publication date

January 1995

DOI

10.1109/TEST.1995.529816

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Abstract

NUMBER OF PAGES: xii+1011This paper presents implementation and test experiments of a current monitoring technique for on-line detection and correction of transient faults in CMOS static RAMs. This technique combines built-in current sensing (BICS) with parity code to achieve zero detection latency and single-bit error correction

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Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments

Abstract

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Upset-tolerant CMOS SRAM using current monitoring: prototype and test experiments

Abstract

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