A test methodology applied to cellular logic programmable gate arrays

ISBN: 3540584196This paper describes an approach for testing a class of programmable logic devices called Cellular Programmable Gate Arrays. The flexibility in the selection of logic functions and the high number of interconnections in this class of devices turns test a complex task. It has led to the proposition of an efficient test procedure based on some functions properties. The regularity of the procedure permits that all logic cells in the device can be tested completely for functional faults at the same time, whenever is possible. It provides a reduced number of reprogramming times during test mode and a possibility of testing more devices in a defined period of time