Add to ORKGISBN: 076951944XThe successful application of model-checking to industrial designs requires methods for reducing the complexity of the model. This paper presents an original strategy, for a well identified class of circuit behaviors; by running an appropriate symbolic simulation pattern before the actual proof of a temporal formula, an important FSM model simplification can be obtained. The actual model reduction step is formalized and illustrated. This method has been implemented within the CMU version of the SMV model checking tool and validated on a large industrial design
A logic simulator can prove the correctness of a digital circuit when it can be shown that only circ...
Abstract: In this paper, we defined a new FSM model that based on the synchronous behavior and symbo...
Formal verification of high-level SystemC designs is an im-portant and challenging problem. Recent w...
International audienceThe successful application of model-checking to industrial designs calls for a...
The successful application of model-checking to industrial designs calls for a minimal set of effici...
Steadily increasing design sizes, make the verification a bottleneck in modern design flows of digit...
Abstract: The successful application of model-checking to industrial designs calls for a minimal set...
Model checking is an automatic technique for verifying sequential circuit designs and protocols. An ...
The design of correct computer systems is extremely difficult. However, it is also a very important ...
. We present a new approach to the verification of hardware systems with data dependencies using tem...
The program MOSSYM simulates the behavior of a MOS circuit represented as a switch-level network sym...
AbstractThe design of correct computer systems is extremely difficult. However, it is also a very im...
In hardware verification, the introduction of symbolic model checking has been considered a break-th...
Abstract. We present a new approach to the verification of hardware systems with data dependencies u...
The development of embedded systems requires formal analysis of models such as those described with ...
A logic simulator can prove the correctness of a digital circuit when it can be shown that only circ...
Abstract: In this paper, we defined a new FSM model that based on the synchronous behavior and symbo...
Formal verification of high-level SystemC designs is an im-portant and challenging problem. Recent w...
International audienceThe successful application of model-checking to industrial designs calls for a...
The successful application of model-checking to industrial designs calls for a minimal set of effici...
Steadily increasing design sizes, make the verification a bottleneck in modern design flows of digit...
Abstract: The successful application of model-checking to industrial designs calls for a minimal set...
Model checking is an automatic technique for verifying sequential circuit designs and protocols. An ...
The design of correct computer systems is extremely difficult. However, it is also a very important ...
. We present a new approach to the verification of hardware systems with data dependencies using tem...
The program MOSSYM simulates the behavior of a MOS circuit represented as a switch-level network sym...
AbstractThe design of correct computer systems is extremely difficult. However, it is also a very im...
In hardware verification, the introduction of symbolic model checking has been considered a break-th...
Abstract. We present a new approach to the verification of hardware systems with data dependencies u...
The development of embedded systems requires formal analysis of models such as those described with ...
A logic simulator can prove the correctness of a digital circuit when it can be shown that only circ...
Abstract: In this paper, we defined a new FSM model that based on the synchronous behavior and symbo...
Formal verification of high-level SystemC designs is an im-portant and challenging problem. Recent w...