Improving the performance of asymmetric multicore processors by transactions’ migration and the adaptation of the cache subsystem

Postojeći pravci razvoja računarstva imaju za cilj da se performanse računarskih sistema podignu na što viši nivo, da bi se zadovoljile potrebe za obradom velike količine podataka...Existing trends in computer design aim to raise the performance of computer systems to the highest possible level in order to meet the needs for processing large amounts of data. Attention is focused on the design of a processor as the main actor in the data processing process. Improvement trends in processor performance predicted by Moore’s Law has been slowing down recently due to physical limitations of semiconductor technology and increasing performance is getting harder and harder. This problem is attempted to be compensated by various techniques aimed at improving performance without increasing transistor and power consumption. In this thesis, asymmetric multicore processors with support for transactional memory are considered. Two new techniques have been proposed to increase the performance of such processors. One technique aims to reduce transaction congestion due to high parallelism by migrating transactions to a faster core. The transactions that contribute the most to an occurrence of congestion are selected for migration. Executing them on a faster core reduces their chances of conflict with other transactions and thus increases the chance of avoiding congestion. Another technique adjusts the cache subsystem to reduce caches’ access latency and to reduce the chances of false conflicts while reducing the number of transistors required to implement the cache. This can be achieved by using small and simple caches. Detailed implementation proposals are given for both techniques. Prototypes of these techniques were made in the Gem5 simulator, which models processor’s system in detail. Using prototypes, the proposed techniques were evaluated by simulating a large number of applications from a standard benchmark set for transactional memory. The analysis of the simulation results gave suggestions on how and when the proposed techniques should be used