NUMBER OF PAGES: xiii+394We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. These complete and optimized representations help the designer to understand the accurate behaviour of the circuit. This deep understanding is a prerequisite for any verification or test process. An example is fully presented to illustrate our method. This simple pipelined processor comes from our experience in computer architecture and digital design education
International audienceThis paper presents the case study proposed to 3rd year students in our depart...
Verification has become one of the major bottlenecks in today’s circuit and system design. Up to 80 ...
AbstractWe show how the unique character of logic programming can be exploited for the purpose of sp...
ISBN: 8372830959A deep understanding of circuit behaviour is a prerequisite for any verification pro...
The paper describes a new technique for extracting clock level finite state machines (FSMs) from tra...
Representing finite state systems by means of finite state machines is a common approach in VLSI cir...
In this dissertation, the use of extracted functional models in some typical Computer-Aided-Design a...
This thesis has explored how structural techniques can be applied to the problem of formal verificat...
Abstract--State space traversal algorithms for Finite State Machine (FSM) models of synchronous sequ...
[[abstract]]Reachability analysis is a fundamental technique in the synthesis,verification of VLSI c...
A simplified method of designing Finite State Machines (FSM) is described, which is suitable for stu...
A logic simulator can prove the correctness of a digital circuit if it can be shown that only circui...
There is a well recognized need for accurate timing verification tools. Such tools, however, are sus...
The design of state-of-the-art digital circuits often involves interacting state machines with very ...
Practically, any digital system includes sequential blocks represented using a model of finite state...
International audienceThis paper presents the case study proposed to 3rd year students in our depart...
Verification has become one of the major bottlenecks in today’s circuit and system design. Up to 80 ...
AbstractWe show how the unique character of logic programming can be exploited for the purpose of sp...
ISBN: 8372830959A deep understanding of circuit behaviour is a prerequisite for any verification pro...
The paper describes a new technique for extracting clock level finite state machines (FSMs) from tra...
Representing finite state systems by means of finite state machines is a common approach in VLSI cir...
In this dissertation, the use of extracted functional models in some typical Computer-Aided-Design a...
This thesis has explored how structural techniques can be applied to the problem of formal verificat...
Abstract--State space traversal algorithms for Finite State Machine (FSM) models of synchronous sequ...
[[abstract]]Reachability analysis is a fundamental technique in the synthesis,verification of VLSI c...
A simplified method of designing Finite State Machines (FSM) is described, which is suitable for stu...
A logic simulator can prove the correctness of a digital circuit if it can be shown that only circui...
There is a well recognized need for accurate timing verification tools. Such tools, however, are sus...
The design of state-of-the-art digital circuits often involves interacting state machines with very ...
Practically, any digital system includes sequential blocks represented using a model of finite state...
International audienceThis paper presents the case study proposed to 3rd year students in our depart...
Verification has become one of the major bottlenecks in today’s circuit and system design. Up to 80 ...
AbstractWe show how the unique character of logic programming can be exploited for the purpose of sp...