Thèse CIFRE réalisée en collaboration avec le LTM-CNRS, Grenoble, France et la société STMicroelectronics, Crolles, FranceAs the dimensions of CMOS transistors shrink, parasitic effects become more significant and theelectrical device properties are perturbated. Silicon and silicon oxide materials are no more suitable for the gate module, and it is expected that metals and high-k dielectric will replace them soon. This work focuses on plasma etching of metal gate polysilicon/TiN/HfO2 for their integration in 45 nmand 32 nm technology nodes.Halogen-based plasmas and plasma-surface interactions have been analyzed by mass spectrometry, Xray photoelectron spectroscopy and morphological characterization techniques (SEM, TEM, AFM). This allowed t...
New materials have to be introduced in the gate stack in order to ensure the miniaturization of CMOS...
International audienceIn ULSI technology, plasma etch processes at the front end level are becoming ...
New materials have to be introduced in the gate stack in order to ensure the miniaturization of CMOS...
Thèse CIFRE réalisée en collaboration avec le LTM-CNRS, Grenoble, France et la société STMicroelectr...
Thèse CIFRE réalisée en collaboration avec le LTM-CNRS, Grenoble, France et la société STMicroelectr...
With the reduction of devices dimensions and the introduction of new gate materials such as metals a...
With the reduction of devices dimensions and the introduction of new gate materials such as metals a...
With the reduction of devices dimensions and the introduction of new gate materials such as metals a...
With the reduction of devices dimensions and the introduction of new gate materials such as metals a...
With the reduction of CMOS devices dimensions, we have to change the conventional CMOS gate poly-sil...
This work focuses on the understanding of the mechanisms involved in plasma etching processes used t...
This work focuses on the understanding of the mechanisms involved in plasma etching processes used t...
This work focuses on the understanding of the mechanisms involved in plasma etching processes used t...
International audienceIn ULSI technology, plasma etch processes at the front end level are becoming ...
New materials have to be introduced in the gate stack in order to ensure the miniaturization of CMOS...
New materials have to be introduced in the gate stack in order to ensure the miniaturization of CMOS...
International audienceIn ULSI technology, plasma etch processes at the front end level are becoming ...
New materials have to be introduced in the gate stack in order to ensure the miniaturization of CMOS...
Thèse CIFRE réalisée en collaboration avec le LTM-CNRS, Grenoble, France et la société STMicroelectr...
Thèse CIFRE réalisée en collaboration avec le LTM-CNRS, Grenoble, France et la société STMicroelectr...
With the reduction of devices dimensions and the introduction of new gate materials such as metals a...
With the reduction of devices dimensions and the introduction of new gate materials such as metals a...
With the reduction of devices dimensions and the introduction of new gate materials such as metals a...
With the reduction of devices dimensions and the introduction of new gate materials such as metals a...
With the reduction of CMOS devices dimensions, we have to change the conventional CMOS gate poly-sil...
This work focuses on the understanding of the mechanisms involved in plasma etching processes used t...
This work focuses on the understanding of the mechanisms involved in plasma etching processes used t...
This work focuses on the understanding of the mechanisms involved in plasma etching processes used t...
International audienceIn ULSI technology, plasma etch processes at the front end level are becoming ...
New materials have to be introduced in the gate stack in order to ensure the miniaturization of CMOS...
New materials have to be introduced in the gate stack in order to ensure the miniaturization of CMOS...
International audienceIn ULSI technology, plasma etch processes at the front end level are becoming ...
New materials have to be introduced in the gate stack in order to ensure the miniaturization of CMOS...