ISBN :978-0-387-73660-0New technologies present a widely range of challenges in the design of standard-cell libraries, layout generation and validation of macro-blocks. Thus, the development of new tools being able to deal with these challenges is mandatory. This work presents a transistor placement technique using genetic algorithm associated to analytical programming. The genetic algorithm is used to reduce the search space of possible solutions while analytical equations are used to find out the position of each transistor in the layout
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
An important stage in circuit design is placement, where components are assigned to physical locatio...
A new genetic algorithm for the macro cell placement problem is presented. The algorithm is based on...
This research investigates the application of the Genetic Algorithm for four VLSI layout problems, G...
Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this probl...
The topic of this Ph.D. thesis is the application of evolution-based algorithms (EAs) to various hig...
Practical analog layout synthesis techniques have been the subject of active research for the past t...
Abstract — Genetic algorithms have proven to be a well-suited technique for solving selected combina...
This paper addresses the optimization of cell placement step in VLSI circuit design [1]. A novel hyb...
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with signific...
In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm...
This paper presents a novel genetic algorithm for analog module placement. It is based on a generali...
This paper presents an integrated approach of simulated annealing (SA) and genetic algorithm (GA) fo...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
In this paper we present a timing -driven placer for standard-cell IC design. The placement algorith...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
An important stage in circuit design is placement, where components are assigned to physical locatio...
A new genetic algorithm for the macro cell placement problem is presented. The algorithm is based on...
This research investigates the application of the Genetic Algorithm for four VLSI layout problems, G...
Analog macrocell placement is an NP-hard problem. This paper presents an attempt to solve this probl...
The topic of this Ph.D. thesis is the application of evolution-based algorithms (EAs) to various hig...
Practical analog layout synthesis techniques have been the subject of active research for the past t...
Abstract — Genetic algorithms have proven to be a well-suited technique for solving selected combina...
This paper addresses the optimization of cell placement step in VLSI circuit design [1]. A novel hyb...
Genetic Algorithms have worked fairly well for the VLSI cell placement problem, albeit with signific...
In this paper we present a timing-driven placer for standard-cell IC design. The placement algorithm...
This paper presents a novel genetic algorithm for analog module placement. It is based on a generali...
This paper presents an integrated approach of simulated annealing (SA) and genetic algorithm (GA) fo...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
In this paper we present a timing -driven placer for standard-cell IC design. The placement algorith...
We employ two iterative heuristics for the optimization of VLSI standard cell placement. These heuri...
An important stage in circuit design is placement, where components are assigned to physical locatio...
A new genetic algorithm for the macro cell placement problem is presented. The algorithm is based on...