High-level symbolic simulation for automatic model extraction
- Ouchet, F.
- Borrione, D.
- Morin-Allory, Katell
- Pierre, Laurence
Publication date
April 2009
DOI Publisher
Institute of Electrical and Electronics Engineers (IEEE)Abstract
ISBN : 978-1-4244-3341-4International audienceThis paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. The generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ancestor Theosim; it brings various improvements e.g., with regard to arrays and other complex data types
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